advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 144-mbit qdr?-ii sram 2-word burst architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-16238 rev. ** revised june 21, 2007 features separate independent read and write data ports ? supports concurrent transactions 333 mhz clock for high bandwidth 2-word burst on all accesses double data rate (ddr) interfaces on both read and write ports (data transferred at 666 mhz) at 333 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for output data (c and c ) to minimize clock skew and flight ti me mismatches echo clocks (cq and cq ) simplify data capture in high speed systems single multiplexed address input bus latches address inputs for read and write ports separate port selects for depth expansion synchronous internally self timed writes qdr?-ii operate s with 1.5 cycle read la tency when doff is asserted high operates similar to qdr i device with 1 cycle read latency when doff is asserted low available in 8, x9, x18, and x36 configurations full data coherency providing most current data core vdd = 1.8v(0.1v); io vddq = 1.4v to vdd available in 165-ball fbga package (15 x 17 x 1.4 mm) offered in both pb-free and non pb-free packages variable drive hstl output buffers jtag 1149.1 compatible test access port phase locked loop (pll) for accurate data placement configurations cy7c1610kv18 ? 16m x 8 cy7c1625kv18 ? 16m x 9 cy7c1612kv18 ? 8m x 18 cy7c1614kv18 ? 4m x 36 functional description the cy7c1610kv18, cy7c1625kv18, cy7c1612kv18, and cy7c1614kv18 are 1.8v synchronous pipelined srams, equipped with qdr-ii architecture . qdr-ii architecture consists of two separate ports to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. qdr-ii architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that exists with common io devices. each port is accessed through a common address bus. the read address is latched on the rising edge of the k clock and the write address is latched on the rising edge of the k clock. accesses to the qdr-ii read and write ports are completely independent of one another. to maximize data throughput, both read and write ports are equipped with ddr interfaces. each address location is associated with two 8-bit words (cy7c1610kv18), 9-bit words (cy7c1625kv18), 18-bit words (cy7c1612kv18), or 36-bit words (cy7c1614kv18) that burst sequ entially into or out of the device. because data is transferred into and out of the device on every rising edge of input clocks (k and k and c and c ), memory bandwidth is maximized while simplifying system design by eliminating bus turn arounds. port selects for each port enable depth expansion. port selects allow each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c (or k or k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide parameter 333 mhz 300 mhz 250 mhz 200 mhz unit maximum operating frequency 333 300 250 200 mhz maximum operating current x8/x9 850 780 680 580 ma x18 870 810 700 590 x36 1060 980 850 710
advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 document #: 001-16238 rev. ** page 2 of 8 overview figure 1. logic block diagram (cy7c1610kv18) figure 2. logic block diagram (cy7c1625kv18) clk a (22:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logic address register reg. reg. reg. 8 23 8 16 8 nws [1:0] v ref write add. decode 8 a (22:0) 23 c c 8 8m x 8 array 8m x 8 array write reg write reg cq cq 8 doff block diagram clk a (22:0) gen. k k control logic address register d [8:0] read add. decode read data reg. rps wps q [8:0] control logic address register reg. reg. reg. 9 23 9 18 9 bws [0] v ref write add. decode 9 a (22:0) 23 c c 9 8m x 9 array 8m x 9 array write reg write reg cq cq 9 doff block diagram
advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 document #: 001-16238 rev. ** page 3 of 8 figure 3. logic block diagram (cy7c1612kv18) figure 4. logic block diagram (cy7c1614kv18) clk a (21:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps q [17:0] control logic address register reg. reg. reg. 18 22 18 36 18 bws [1:0] v ref write add. decode 18 a (21:0) 22 c c 18 4m x 18 array 4m x 18 array write reg write reg cq cq 18 doff block diagram clk a (20:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps q [35:0] control logic address register reg. reg. reg. 36 21 36 72 36 bws [3:0] v ref write add. decode 36 a (20:0) 21 c c 36 2m x 36 array 2m x 36 array write reg write reg cq cq 36 doff block diagram
advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 document #: 001-16238 rev. ** page 4 of 8 pin configurations 165-ball fbga (15 x 17 x 1.4 mm) pinout table 1. cy7c1610kv18 (16m x 8) [1] table 2. cy7c1625kv18 (16m x 9) [1] 23 4567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc aa nws 1 k wps a nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc/288m k nws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q6 nc d7 d6 v dd a 891011 nc aa rps cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc nc nc a 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc aa nck wps a nc nc nc nc nc tdo nc nc d6 nc nc nc tck nc nc a nc/288m k bws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q5 nc v ddq nc nc nc nc q8 a v ddq v ss v ddq v dd v dd q6 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d5 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q7 nc d8 d7 v dd a 891011 q0 aa rps cq a nc nc q4 v ss nc nc d4 nc v ss nc q3 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d2 v ddq nc q2 nc v ddq v ddq nc v ss nc d1 nc tdi tms v ss a nc a nc d3 nc zq nc q1 nc nc d0 nc a note 1. nc/288m is not connected to the die and can be tied to any voltage level.
advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 document #: 001-16238 rev. ** page 5 of 8 165-ball fbga (15 x 17 x 1.4 mm) pinout table 3. cy7c1612kv18 (8m x 18) [1] table 4. cy7c1614kv18 (4m x 36) [1] 234 56 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc aa bws 1 k wps nc/288m q9 d9 nc nc nc tdo nc nc d13 nc nc nc tck nc d10 a nc k bws 0 v ss aaa q10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q11 d12 v ddq d14 q14 d16 q16 q17 a v ddq v ss v ddq v dd v dd q13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d11 v ss nc v ss q12 nc v ref v ss v dd v ss v ss a v ss c nc q15 nc d17 d15 v dd a 891011 q0 aa rps cq a nc nc q8 v ss nc q7 d8 nc v ss nc q6 d5 nc nc v ref nc q3 v ddq nc v ddq nc q5 v ddq v ddq v ddq d4 v ddq nc q4 nc v ddq v ddq nc v ss nc d2 nc tdi tms v ss a nc a d7 d6 nc zq d3 q2 d1 q1 d0 nc a 23 4 567 1 a b c d e f g h j k l m n p r a cq q27 d27 d28 d34 doff q33 nc/288m a bws 2 k wps bws 1 q18 d18 q30 d31 d33 tdo q28 d29 d22 d32 q34 q31 tck d35 d19 a bws 3 k bws 0 v ss aaa q19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q20 d21 v ddq d23 q23 d25 q25 q26 a v ddq v ss v ddq v dd v dd q22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d20 v ss q29 v ss q21 d30 v ref v ss v dd v ss v ss a v ss c q32 q24 q35 d26 d24 v dd a 891011 q0 aa rps cq a d17 q17 q8 v ss d16 q7 d8 q16 v ss d15 q6 d5 d9 q14 v ref q11 q3 v ddq q15 v ddq d14 q5 v ddq vddq v ddq d4 v ddq d12 q4 q12 v ddq v ddq d11 v ss d10 d2 q10 tdi tms v ss a q9 a d7 d6 d13 zq d3 q2 d1 q1 d0 q13 a
advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 document #: 001-16238 rev. ** page 6 of 8 ordering information not all of the speed, package and temper ature ranges are available. contact your local sales representative or visit www.cypress.com for actual products offered. table 5. ordering information speed (mhz) ordering code package diagram package type operating range 333 cy7c1610kv18-333bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial cy7c1625kv18-333bzc cy7c1612kv18-333bzc cy7c1614kv18-333bzc cy7c1610kv18-333bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-333bzxc cy7c1612kv18-333bzxc cy7c1614kv18-333bzxc cy7c1610kv18-333bzi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) industrial cy7c1625kv18-333bzi cy7c1612kv18-333bzi cy7c1614kv18-333bzi cy7c1610kv18-333bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-333bzxi cy7c1612kv18-300bzxi cy7c1614kv18-333bzxi 300 cy7c1610kv18-300bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial cy7c1625kv18-300bzc cy7c1612kv18-300bzc cy7c1614kv18-300bzc cy7c1610kv18-300bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-300bzxc cy7c1612kv18-300bzxc cy7c1614kv18-300bzxc cy7c1610kv18-300bzi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) industrial cy7c1625kv18-300bzi cy7c1612kv18-300bzi cy7c1614kv18-300bzi cy7c1610kv18-300bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-300bzxi cy7c1612kv18-300bzxi cy7c1614kv18-300bzxi
advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 document #: 001-16238 rev. ** page 7 of 8 250 cy7c1610kv18-250bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial cy7c1625kv18-250bzc cy7c1612kv18-250bzc cy7c1614kv18-250bzc cy7c1610kv18-250bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-250bzxc cy7c1612kv18-250bzxc CY7C1614KV18-250BZXC cy7c1610kv18-250bzi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) industrial cy7c1625kv18-250bzi cy7c1612kv18-250bzi cy7c1614kv18-250bzi cy7c1610kv18-250bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-250bzxi cy7c1612kv18-250bzxi cy7c1614kv18-250bzxi 200 cy7c1610kv18-200bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial cy7c1625kv18-200bzc cy7c1612kv18-200bzc cy7c1614kv18-200bzc cy7c1610kv18-200bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-200bzxc cy7c1612kv18-200bzxc cy7c1614kv18-200bzxc cy7c1610kv18-200bzi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) industrial cy7c1625kv18-200bzi cy7c1612kv18-200bzi cy7c1614kv18-200bzi cy7c1610kv18-200bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1625kv18-200bzxi cy7c1612kv18-200bzxi cy7c1614kv18-200bzxi table 5. ordering information (continued) speed (mhz) ordering code package diagram package type operating range
document #: 001-16238 rev. ** revised june 21, 2007 page 8 of 8 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oduct and company names mentioned in this document are the trademarks of their respective holders. advance information cy7c1610kv18, cy7c1625kv18 cy7c1612kv18, cy7c1614kv18 ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7c1610kv18/cy7c1625kv18/cy7c16 12kv18/cy7c1614kv18 144-mbit qdr?-ii sram 2-word burst architecture document number: 001-16238 rev. ecn no. issue date orig. of change description of change ** 1184523 see ecn vkn new data sheet
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